Adv7180-adv7180 init

adv7180_init的实现流程

一,csi0_tvin_io_init

1,csi0_tvin_io_init->csi_port0_iomux_config->camera_ipu1_iomux_config

iomux: imput/output multiplexer 输入输出多路器

camera_ipu1_iomux_config：HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12_WR

HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12_WR

HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13_WR

HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13_WR

HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14_WR

HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14_WR

HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15_WR

HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15_WR

HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16_WR

HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16_WR

HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17_WR

HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17_WR

HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18_WR

HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18_WR

HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19_WR

HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19_WR

HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC_WR

HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC_WR

HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK_WR

HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK_WR

HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC_WR

HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC_WR

二,adv7180_i2c_init

三,adv7180_read_reg

五,adv7180_hard_reset

六,hal_delay_us